A High-Performance Sequential MRU Cache Using Valid-Bit Assistant Search Algorithm

Most recently used (MRU) cache is one of the set-associative caches that emphasize implementation of associativity higher than 2. However, the access time is increased because the MRU information must be fetched before accessing the sequential MRU (SMRU) cache. In this paper, focusing on the SMRU cache with subblock placement, we propose an MRU cache scheme that separates the valid bits from data memory and uses these valid bits to decide to reduce the unnecessary access number of memory banks. By this approach, the probability of the front hits is thus increased, and it significantly helps in improving the average access time of the SMRU cache without valid-bit assistant search especially for large associativity and small subblock size.